Imaging chips that are utilized in a wide range of camera devices are based on CCD arrays. The CCD structure can be viewed as a number of columns that are divided into pixels whose boundaries can be moved to read out the charge by shifting the charge down the columns. The boundaries of the pixels and the charge shifting mechanism are implemented with a plurality of gates that overlie the portion of the substrate in which the columns are located. Each pixel on the chip has a plurality of gates. These gates are used to shift the charge along the columns and eventually to an amplifier that converts the charge to a voltage and then buffers the voltage off of the chip.
In low light applications, the amount of charge generated by each pixel is quite small; hence, a high degree of amplification is needed. If the charge to voltage conversion is performed on the CCD substrate, the amplifier is limited to the devices that can be constructed using the CCD fabrication process. CCDs require high charge-transfer efficiency. To achieve this efficiency, CCDs are fabricated using specialized processes that minimize imperfections in the semiconductor material. Most logic circuitry relies on CMOS fabrication techniques. In general, the fabrication processes used to produce CCD and CMOS imagers are incompatible. For example, the conventional CMOS fabrication processes require complex processes that lead to unacceptable imperfections in the underlying semiconductor materials. While generally acceptable in CMOS devices, these imperfections typically reduce the efficiency of CCD devices to unacceptable levels.
CCD devices are typically manufactured in an NMOS or PMOS process. If the CCD is an NMOS device, NMOS FET transistors, N type JFETs, NPN bipolar transistors with their bases shorted to ground, and PNP bipolar transistors can be fabricated; however, NPN transistors with floating bases, P type JFETs, and PMOS FETs cannot be fabricated. As a result, the circuits that can be fabricated on the CCD chip itself are limited to source follower type circuits that provide very little voltage gain. The resultant signals are in the microvolt range, and hence, are easily contaminated with noise when the signals are transferred off of the chip to another amplification stage. As a result, designs that utilize an off-chip amplifier have been developed.
The off-chip amplifier is typically a CTIA. The gain of the amplifier is inversely proportional to the parasitic capacitance of the pad and the silicon area connected to the pad. The noise of the amplifier is proportional to the parasitic capacitance of the pad and the silicon area connected to the pad. This capacitance can be relatively large, since the pad must be large enough to be connected to the substrate on which the amplifier is located by solder bump. Hence, the maximum gain available with an off-chip CTIA is also limited.